The prior art teaches the formation of integrated circuits which utilize one or more junction field effect transistor (JFET) devices. The JFET device includes a junction formed under a gate conductor. Rather than use an insulated gate, as is conventional MOSFET-type devices, a field is applied by the junction acting as a gate. Current flows between the source and drain regions in a doped semiconductor region located under the gate. Through application of a voltage to the gate conductor, a region of depleted charge forms in the doped semiconductor region so as to pinch off the conducting path and restrict the flow of current. Because of the lack of available mobile charge, the depletion region behaves as an insulating structure.
The conventional JFET device is an attractive circuit for use in analog designs. The device is simple to form and operate. However, such JFET devices suffer from a noted drawback in that short channel effects are difficult to control. Additionally, the typical manufacture of JFET devices is incompatible with mainstream CMOS fabrication techniques. There is accordingly a need in the art to address the foregoing and other issues to provide a JFET device of improved configuration and operation, wherein manufacture of the device is compatible with CMOS techniques.